Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require many hundreds of connections to external devices.
Semiconductor chips commonly have been connected to electrical traces on mounting substrates by one of three methods: wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the semiconductor chip is positioned on a substrate with a bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate. Individual gold or aluminum wires are connected between the contacts on the semiconductor chip and current conducting pads on the substrate. In tape automated bonding a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the semiconductor chip and substrate, and the individual leads are bonded to the contacts on the chip and to the current conducting pads on the substrate. In both wire bonding and conventional tape automated bonding, the current conducting pads on the substrate are arranged outside of the area covered by the semiconductor chip, so that the wires or leads fan out from the chip to the surrounding current conducting pads. The area covered by the subassembly as a whole is considerably larger than the area covered by the chip. This makes the entire assembly substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with semiconductor chips having contacts disposed in rows extending along the periphery of the chip. They generally do not lend themselves to use with chips having contacts disposed in a so-called area array, i.e., a grid-like pattern covering all or a substantial portion of the chip front surface.
In the flip-chip mounting technique, the contact-bearing surface of the semiconductor chip faces towards the substrate. Each contact on the semiconductor chip is joined by a solder bond to the corresponding current carrying pad on the substrate, as by positioning solder balls on the substrate or contacts of the semiconductor chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems with thermal stress. The solder bonds between the contacts on the semiconductor chip and the current carrying pads on the substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the semiconductor chip before attaching it to the substrate, and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous semiconductor chips.
Numerous attempts have been made to solve the foregoing problem. Useful solutions are disclosed in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266. Preferred embodiments of the structures disclosed in these patents incorporate flexible, sheet-like structures referred to as “interposers” or “chip carriers.” The preferred chip carriers have a plurality of terminals disposed on a flexible, sheet-like top layer. In use, the interposer is disposed on the front or contact-bearing surface of the chip with the terminals facing upwardly, away from the chip. The terminals are then connected to the contacts of the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to the contacts on the semiconductor chip, using a tool engaged with the lead. The completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate. Because the leads and the dielectric layer of the chip carrier are flexible, the terminals on the chip carrier can move relative to the contacts on the semiconductor chip without imposing significant stresses on the bonds between the leads and the contacts on the semiconductor chip, or on the bonds between the terminals of the chip carrier and the substrate. Thus, the assembly can compensate for thermal effects. Moreover, the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the semiconductor chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the semiconductor chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip, and also facilitates movement of the terminals relative to the chip in directions parallel to the chip surface. The compliant structure further enhances the resistance of the assembly to thermal stresses during use, and facilitates engagement between the subassembly and a test fixture during manufacture. Thus, a test fixture incorporating numerous electrical contacts can be engaged with all of the terminals in the subassembly despite minor variations in the height of the terminals. The subassembly can be tested before it is bonded to a substrate so as to provide a tested, known, good part to the substrate assembly operation. This in turn provides very substantial economic and quality advantages.
U.S. Pat. No. 5,455,390 describes a further improvement. Components according to preferred embodiments of the '390 patent use a flexible, dielectric top sheet. A plurality of terminals are mounted on the top sheet. A support layer is disposed underneath the top sheet, the support layer having a bottom surface remote from the top sheet. A plurality of electrically conductive, elongated leads are connected to the terminals on the top sheet and extend generally side by side downwardly from the terminals through the support layer. Each lead has a lower end at the bottom surface of the support layer. The lower ends of the leads have conductive bonding materials as, for example, eutectic bonding metals. The support layer surrounds and supports the leads.
Components of this type can be connected to microelectronic elements such as semiconductor chips or wafers by juxtaposing the bottom surface of the support layer with the contact-bearing surface of the semiconductor chip so as to bring the lower ends of the leads into engagement with the contacts on the chip, and then subjecting the assembly to elevated temperature and pressure conditions. All of the lower ends of the leads bond to the contacts on the semiconductor chip substantially simultaneously. The bonded leads connect the terminals of the top sheet with the contacts on the semiconductor chip. The support layer desirably is either formed from a relatively low-modulus, compliant material, or else is removed and replaced after the lead-bonding step with such a compliant material. In the finished assembly, the terminals on the relatively flexible dielectric top sheet desirably are movable with respect to the contacts on the semiconductor chip to permit testing and to compensate for thermal effects. However, the components and methods of the '390 patent provide further advantages, including the ability to make all of the bonds to the chip or other component in a single lamination-like process step.
U.S. Pat. No. 5,518,964, issued on U.S. patent application Ser. No. 08/271,768, the disclosure of which is hereby incorporated by reference herein, discloses still further improvements. Preferred methods according to the '964 patent include the steps of providing a dielectric connection component or first element having a plurality of terminals, a first surface and a plurality of elongated, flexible leads extending along the first surface, each such lead having a terminal end attached to one of the terminals and a tip end offset from the terminal end in a generally horizontal direction parallel to the first surface. Desirably, the tip ends of all the leads are attached to an associated one of the contacts on a second element, such as a microelectronic device. The preferred methods also include the step of simultaneously forming all of the leads by moving all of the tip ends of the leads relative to the terminal ends thereof and relative to the first element so as to bend the tip ends away from the first element. Desirably the step of moving the tip ends of the respective leads relative to their terminal ends includes the step of moving the second element relative to the first element. The first and second elements desirably move in a vertical direction, away from one another, and may also move in horizontal directions parallel to the surfaces of the elements so as to bend the tip end of each lead horizontally towards its own terminal end and vertically away from the terminal end. The net effect is to deform the leads towards formed positions in which the leads extend generally vertically downwardly, away from the first element. These methods may also include the step of injecting a flowable, desirably compliant dielectric material around the leads after the lead-forming step and then curing the flowable material so as to form a dielectric support layer around the leads.
In particularly preferred methods according to the '964 patent application, one element is a flexible, dielectric top sheet having terminal structures thereon, and the other element includes one or more semiconductor chips. The resulting assembly thus includes the dielectric top sheet with the terminal structures connected to the associated contacts of the semiconductor chip or chips by the vertically-extending, curved flexible leads, the dielectric top sheet being spaced apart from the semiconductor chip or chips by the dielectric support layer. The terminal structures can be connected to a substrate such as a circuit panel to thereby provide electrical current communication to the contacts on the semiconductor chip or chips. Each terminal structure on the dielectric top sheet is movable with respect to the contacts in the semiconductor chip in horizontal directions parallel to the chip, as well as in vertical directions towards and away from the chip, to take up differences in thermal expansion between the chip and substrate and to facilitate testing and assembly.
The step of attaching the tip ends of the leads to the second element desirably includes the step of bonding the tip ends of the leads to the contacts on the semiconductor chip or chips while the leads are in their initial, undeformed positions. For example, a dielectric sheet having the leads disposed in generally horizontal orientation on its bottom surface may be juxtaposed with a chip or wafer so that the tip ends of the leads are engaged with the contacts of the chip or wafer. Thus, all of the tip ends are bonded simultaneously to the chip contacts. A single simultaneous bonding operation may bond hundreds or thousands of leads. Because the leads are in their initial, undeformed positions when bonded to the contacts, the positions of the lead tips are well controlled at this stage. Preferably, the tip ends of the leads are releasably bonded to the dielectric top sheet. This facilitates registration of the lead tips contacts on the semiconductor chips. As the top sheet is moved upwardly away from the chip or wafer, the tip ends of the leads are released from the top sheet. The '964 patent also discloses other processes, including processes in which the leads are initially attached to the chip or wafer, and wherein the chip or wafer is engaged with dielectric sheet or other element having contacts thereon and the tip ends of the leads are bonded to the contacts. Although the teachings of the '964 patent can be applied in manufacture of many different products, one product taught in the '964 patent is a so-called “chip size package”. The finished assembly, with the top sheet, terminals and compliant dielectric support layer, can be mounted within an area of a substrate substantially the same as that required to mount the chip itself.